The paper “PANIC: A High-Performance Programmable NIC for Multi-tenant Networks” (OSDI 2020) introduces a novel programmable NIC design—PANIC—to address the limitations of current SmartNICs in multi-tenant data center environments.
Summary*
PANIC is designed to support:
- High throughput and low latency
- Flexible and dynamic offload chaining
- Support for heterogeneous offload engines (hardware accelerators, embedded CPUs, FPGAs)
- Multi-tenant isolation
- Offloads with variable or sub-line-rate performance
Key Components of PANIC
- RMT Pipeline: Uses match-action tables (like in programmable switches) to determine offload chains per-packet.
- Central Scheduler: Ensures fair scheduling, load balancing, and tenant isolation.
- Switching Fabric: High-bandwidth interconnect (crossbar-based) for routing between offloads at line rate.
- Compute Units: Encapsulated offloads, which can be:
- Hardware accelerators (e.g., AES, SHA)
- Embedded RISC-V cores for general-purpose tasks
Evaluation and Results
- Prototyped on an FPGA using the Alpha Data ADM-PCIE-9V3 SmartNIC
- FPGA: Xilinx Virtex UltraScale+ VU3P-2
- Demonstrated:
- 100 Gbps throughput
- Sub-microsecond scheduling latency (<0.8 μs)
- Better isolation and performance over pipeline-based NICs
- Example Offloads:
- AES-256 encryption (HW: 38.4 Gbps vs CPU: 0.154 Gbps)
- SHA1 authentication (HW: 113 Gbps vs CPU: 0.192 Gbps)
- Neural Network inference (HW: 120 Gbps, 66 ns delay)
Which SmartNICs are used?
- The PANIC design was prototyped on the FPGA-based Alpha Data ADM-PCIE-9V3 SmartNIC, equipped with:
- Xilinx UltraScale+ FPGA (VU3P-2)
- No commercial ASIC SmartNIC (like Mellanox BlueField or Netronome) was used.
- PANIC is intended for eventual ASIC implementation, and their design aligns with ASIC feasibility analysis (e.g., crossbar, PIFO, etc.).
Why use Alpha Data ADM-PCIE-9V3?
- Offers FPGA reconfigurability for prototyping
- Allows integration of:
- Custom RMT pipeline
- Central scheduler
- Compute units (both HW accelerators and RISC-V cores)